system verilog - looking for a CRC implementation in Systemverilog -

all, i'm looking class or module implements crc generator (or checker). create 1 scratch, if there's ready made 1 out there might real time saver :-)

thanks! ran

function byte calc_crc(byte unsigned cmd[]);     bit [7:0] crc, d, c;     int i;     crc = 0;      (i=0; i<cmd.size(); i++) begin             d = cmd[i];             c = crc;             crc[0] = d[7] ^ d[6] ^ d[0] ^ c[0] ^ c[6] ^ c[7];             crc[1] = d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6];             crc[2] = d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[6];             crc[3] = d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[7];             crc[4] = d[4] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[4];             crc[5] = d[5] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[5];             crc[6] = d[6] ^ d[5] ^ d[4] ^ c[4] ^ c[5] ^ c[6];             crc[7] = d[7] ^ d[6] ^ d[5] ^ c[5] ^ c[6] ^ c[7];     //$display("crc result: %h",crc);     end     return crc; endfunction