i have designed asynchrounous asymmetric fifo using vhdl constructs.it generic fifo depth , prog_full parameters. has 32-bit in 16-bit output data width. can find fifo design link here.
top level asymmetric fifo (fifo_wrapper.vhd),is built upon 32-bit asynchronous fifo(async_fifo.vhd). internal fifo (async_fifo) build using logic generic fifo on open cores (http://opencores.org/project,generic_fifos). have added simple testbench try out fifo design.
there issue design not able figure out. fifo design works fine when simulate it, when synthesize , run along other design on hardware erroneous data sometimes. may there corner case not able simulate or thing else?
that's why needs design try , let me know if he/she encounters issues during simulation or after synthesis. thanks
ps: kindly let me know if there other forum can put design public use. thanks
there number of issues point out in relation asynchronous fifo design, based on assumption write , read clocks asynchronous.
a (and the) major problem write side pointer (wp in async_fifo), normal binary counter, transfered , synchronized read side clock without gray encoding. different bits in vector may arrive @ different time in read clock domain, write pointer value can (and time time) different write side value. comparison read pointer (rp) therefore make no sense. binary values transfered on clock domains should gray encoded before transfer , decoded @ arrival. use synchronization 2 flip-flop levels.
the 2 clocks (rd_clk , wr_clk) assumed asynchronous, there single reset (rst), timing may violated when reset deasserted, unless there additional requirements clocking @ time of reset deassert.
an similar clear, there 1 signal use in 2 different clock domains.
suggestion use port naming convention clock domain relationship port cleared indicated in name, naming ports in write clock domain wr_* (e.g. wr_clk_i, wr_clk_we_i, etc., , ports in read clock domain rd_*.
reset asserted low, naming of rst_n nice.
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