verilog - For loop in always block -

i have cache memory module want word addressable have write enable signals bytes.

always @ (posedge clk) begin     //stuff...     if(write) begin         //word accessible         //memdata[lastinindex][lastinoffset] <= lastwritedata;          //supporting byte accessible         if(lastwren[0])             memdata[lastinindex][lastinoffset][7:0] <= lastwritedata[7:0];         if(lastwren[1])             memdata[lastinindex][lastinoffset][15:8] <= lastwritedata[15:8];         if(lastwren[2])             memdata[lastinindex][lastinoffset][23:16] <= lastwritedata[23:16];         if(lastwren[3])             memdata[lastinindex][lastinoffset][31:24] <= lastwritedata[31:24];     end     //more stuff... end 

if writing word memory, can specify bytes should ignored , bytes should written within each word. have tested code , simulates fine. parameterize how many bytes in word (in 64 bit case, there 8 bytes per word). rather copy , paste more identical lines, hoping have sort of loop instantiate logic.

always @ (posedge clk) begin     //stuff...     if(write) begin         //word accessible         //memdata[lastinindex][lastinoffset] <= lastwritedata;          //supporting byte accessible         begin : byte_selection_generate             integer i;             for(i=0; i<bytesperword; i=i+1)                 if(lastwren[i])                     memdata[lastinindex][lastinoffset][i*8+7:i*8] <= lastwritedata[i*8+7:i*8];         end     end     //more stuff... end 

i have parameter called wordsize specifies how many bits each word contains (usually 32 or 64). there parameter parameter bytesperword = wordsize/8. when try compile version, error says i not constant. have tried genvar , generate not allowed in blocks. there way generate hardware want based off of bytesperword parameter, or going have rely on ugly string of `ifdef statements?

the error i not constant getting because verilog not allow part selects dynamic values upper , lower value of range (net[i:j]), allow number of bits in bus dynamically change, not possible in hardware.

however in special case since number of bits being selected constant, can use indexed part select operator, looks like:

memdata[lastinindex][lastinoffset][i*8 +: 8];

this same thing attempting (select 8 bits starting i*8), uses special operator it.