Flip flop implementation with process. [VHDL] -

my question in regards following code:

library ieee; use ieee.std_logic_1164.all;  entity exam port (     i,clk,reset : in std_logic;     q : out std_logic ); end entity;  architecture exam_arc of exam     signal temp_sig : std_logic; begin     process (clk,reset)     begin         if reset = '1'             temp_sig <='0';         elsif clk'event , clk='1'             temp_sig <= i;         end if;         q <= temp_sig;     end process; end exam_arc; 

it seems piece of code simulates d flip flop operates on rising edge of clock, answer [this question taken exam] question claims d flip flop operates on falling edge of clock.

what kind of flip flop vhdl code simulates?

it's trick question. note process wakes on both rising , falling clock edges, , intermediate signal temp_sig assigned on rising_edge.

put semantics of signal assignment (postponed assignment) , see get.

cross check via simulation jim suggests...